“At present, many processor chips have integrated a synchronous serial interface, but there are not many processors based on a three-wire synchronous serial interface. Although the three-wire synchronous communication hardware circuit interface implemented by traditional design methods can meet the general engineering design requirements, under the promotion of the design concept of “low cost, small size, low power consumption and flexibility”, the traditional design obviously does more harm than good .
Authors: Feng Chunyang, Zhang Suinan
In the field of aerospace engineering, long-distance telemetry and remote control such as satellite-to-ground communications are one of the important functions of embedded satellite data management computers. The use of three-wire synchronous serial telemetry and remote control channels to send and receive instructions and data is an important part of the communication link.
At present, many processor chips have integrated a synchronous serial interface, but there are not many processors based on a three-wire synchronous serial interface. Although the three-wire synchronous communication hardware circuit interface implemented by traditional design methods can meet the general engineering design requirements, under the promotion of the design concept of “low cost, small size, low power consumption and flexibility”, the traditional design obviously does more harm than good . Using programmable logic device CPLD/FPGA technology to design and implement the structure of the three-wire synchronous serial communication interface circuit can greatly reduce the system volume, reduce power consumption, and improve design flexibility. At the same time, other logic function modules can be added to them, and they can be easily applied to related embedded systems.
1 Three-wire synchronous serial communication mechanism
In three-wire synchronous serial communication, the sender and receiver must use a common clock source to maintain accurate synchronization between them. In order to achieve accurate synchronization, one of the methods is to use the principle of encoding and decoding, that is, use an encoder at the transmitting end to combine the data to be sent with the transmitting clock, and send it to the receiving end through the transmission line, and then use the decoding at the receiving end. The receiver separates the receiving clock from the data stream. Commonly used codecs include Manchester codec and NRZ-L code. The code pattern used in this article for receiving and sending signals is NRZ-L code.
Three-wire synchronous serial communication mainly includes three signals: sampling signal (also called frame synchronization signal), clock signal and serial data signal. The logical relationship of the sequence is shown in Figure 1.
It can be seen from Figure 1 that when data is received or sent, the frame synchronization signal first triggers an instantaneous start pulse, and then remains active at low level. The clock signal immediately follows, and the data remains stable on the rising edge of the clock signal and starts For sampling and transmission, one bit of character data is sent and received every clock cycle, and serial data is sent and received continuously in batches.
2 Three-wire synchronous serial communication controller interface structure design
2.1 Implementation of hardware circuit interface based on traditional design
In the traditional hardware circuit design of the three-wire synchronous serial communication controller interface, multiple components are needed to realize its functions, including: asynchronous four-bit counter, shift register, 8-bit D flip-flop, AND gate, NAND The main functional devices such as gates and inverters, and the schematic diagram of the interface circuit are implemented in ProteI 99 SE.
The hardware circuit of the three-wire synchronous serial communication controller receiving interface is shown in Figure 2.
As can be seen from Figure 2, the logic control function is realized through different combinations of reset signal rst n, chip selection signal CS, gate control signal strobe and read/write signal RW. Through the counting function of the asynchronous four-bit counter SN54HC161, the shift register SN54HC164 smoothly performs the serial/parallel conversion of data, and locks the 8-bit parallel data through the 8-bit D flip-flop SN54HC374 on the internal bus and waits for the system to receive it. At the output end, an interrupt signal int is generated through the double D flip-flop SN54HC74 to notify the microprocessor in the system to receive data.
The hardware circuit of the three-wire synchronous serial communication controller sending interface is shown in Figure 3.
It can be seen from Figure 3 that the system clock start-clk generates the original sending clock signal code-clk through the frequency divider circuit module, which is used for the clock state control of the circuit. The microprocessor in the system transfers the 8-bit parallel data to be sent through the 8-bit D flip-flop SN54HC377, locks the data in its Q port and waits for transmission, and then under the control of the counting function of the asynchronous four-bit counter SN54HC161, the shift register SN54HC165 performs the data Parallel/serial conversion operation. At the output end, the interrupt signal is generated by the double D flip-flop SN54HC74, and then the one-way bus driver SN54HC244 is used to transmit the frame synchronization signal, clock signal and data.
2.2 Design of interface structure based on CPLD/FPGA
In order to solve the shortcomings of traditional hardware circuit components, large power consumption, large size, etc., it has become a necessity to use CPLD/FPGA technology and combine VHDL hardware description language to design three-wire synchronous serial communication controller interface. Combining three-wire synchronization Serial communication mechanism, designed the internal structure of CPLD/FPGA-based three-wire synchronous serial communication controller interface, and its functional structure is shown in Figure 4.
The internal structure of the entire three-wire synchronous serial communication controller interface is mainly composed of four modules: clock frequency division module, system interface control logic, data receiving module, and data sending module.
The clock frequency division module is mainly used for the data receiving/sending module to generate a synchronous clock signal. The system interface control logic is mainly used for the control of various logic function signals. At the same time, it can also receive the interrupt signal generated by the interrupt arbitration logic module to control the data receiving or sending operation. The data receiving module is the core part of the three-wire synchronous serial communication controller interface for data receiving, and its module structure is shown in Figure 5.
Data receiving process: Under the trigger of the frame synchronization pulse signal, the serial data remains stable when the rising edge of the clock signal rclk arrives, and enters the data receiving module through the rdata signal line. Inside the module, serial data undergoes serial/parallel conversion, and the receiving FIFO is used as a data buffer. The received data is latched in two address registers specified by the VHDL program. One address unit stores the high eight bits of the data, and the other The address unit stores the lower eight bits of the data. When the two address units are full of data, the interface sends a “receive buffer full” receive interrupt flag int to the system. After the system microprocessor responds, all the data is taken out, and the data is paralleled. It is sent to the data bus of the system, and the same operation is repeated until all the data is received continuously, and the data receiving process ends.
The data transmission module is also the core part of the three-wire synchronous serial communication interface for data transmission, and its module structure is shown in Figure 6.
Data transmission process: triggered by the sgate frame synchronization pulse signal, the parallel data on the system data bus remains stable when the rising edge of the clock signal sclk arrives, and the data transmission module starts data transmission. Inside the module, the FIFO data buffer is first sent. When the parallel data is full of the buffer unit, the data sending module sends a “transmission buffer full” transmission interrupt flag int to the system. After the system microprocessor responds, the parallel data is sent from Read in FIFO, after parallel/serial conversion into serial data, the most significant MSB is the first, the least significant LSB is the last, and is sent to the sending data signal line Sdata, sent to the peripheral device interface, repeat the same operation until the sending is completed All data, the data sending process ends.
Based on the introduction of the three-wire synchronous serial communication mechanism, this article first designs the hardware circuit of the three-wire synchronous serial communication interface, and then builds a CPLD/FPGA-based three-wire synchronous serial based on the shortcomings of the traditional circuit design. The interface structure of the communication controller, detailed each functional module and its working principle, the design is reasonable, and meets the actual application requirements. At present, this interface structure module has been successfully applied to an aerospace project and its supporting hardware test platform as a key sub-module in FPGA design.