As consumer Electronic devices continue to decrease in size and increase in complexity, there is a strong need to integrate more and more functions onto a single chip. There are many reasons for this integration. Board design becomes simpler, fewer devices need to be placed, and fewer interconnects to route.

Author: Cirrus Logic

As consumer electronic devices continue to decrease in size and increase in complexity, there is a strong need to integrate more and more functions onto a single chip. There are many reasons for this integration. Board design becomes simpler, fewer devices need to be placed, and fewer interconnects to route.

In a purely digital environment, integration is evolving at breakneck speed. Over the past decade, digital integration has fundamentally changed the system design of consumer electronics such as DVD players, AVRs, and MP3 players. Consumers have repeated the benefits of faster, cheaper and smaller consumer electronic devices. This integration path becomes more difficult when one tries to combine the analog and digital parts of the signal path. Large digital system-on-chip (SoC) ICs have begun to include this analog capability in many consumer electronics applications. The challenges here are extreme. Despite many process improvements, such as deep n-well technology, which isolates analog circuitry from the digital core, designers are ultimately trying to co-locate high-performance analog converters with fast and noisy digital signal processors (DSPs). on the substrate. To date, few devices have brought their true high-performance converters and high-speed DSPs to market. To address this challenge, it is necessary to investigate new converter architectures that are less sensitive to disturbances from on-chip digital circuits.

Traditional switched capacitor architecture

Most modern audio converters use a switched capacitor architecture. Figure 1 shows a block diagram of a simplified switched-capacitor analog-to-digital converter (ADC).

Block Diagram Introduction of Switched Capacitor Analog-to-Digital Converter (ADC)

The architecture of switched capacitor DACs is similar, and although the discussion that follows will focus on ADCs, the analysis also applies to DACs. In the ADC, the input audio signal is sampled to the sampling capacitor tex_C_{s} [/ tex], then transferred to the integrating capacitor tex(C_{i})[/ tex]. A two-phase clock is used where the input is sampled on phi1 and transferred to the integrating capacitor along with the feedback signal ±Vref on phi2. The critical time for this architecture is when the phi1 switch is open and the phi2 switch is closed. This is the point in time when the input signal is sampled and provided to the integrator. Any noise on the input or ground will be sampled and appear in the ADC output. A common technique in converter design is to clock a digital clock so that it occurs after a sampling event.

Block Diagram Introduction of Switched Capacitor Analog-to-Digital Converter (ADC)

The edges of the digital clock will always inject signal-related noise into the substrate, which will find its way to the reference node or the sampling capacitor ground node. As long as a digital edge occurs after the sampling event, no noise is sampled at the ADC input.

In stand-alone converters, this noise management is easy to implement. All clocks usually come from a single source, so ensuring the timing relationship between analog and digital clocks is simple. Even though digital clocks are faster than analog clocks, it is easy to find safe areas to place these digital edges. On a complex DSP, where asynchronous digital cores can run much faster than converters, the problem is much more difficult. Figure 3 shows the nature of the problem.

Block Diagram Introduction of Switched Capacitor Analog-to-Digital Converter (ADC)

Safe times for sampling events cannot be guaranteed. In some solutions, the DSP simply stalls for multiple cycles to create a safe sampling event, as shown by the shaded box in Figure 3. This effectively removes the coupling between the DSP and the converter, but at the cost of MIPS. Assuming a typical 6.144 MHz converter clock and 98.3 MHz DSP clock (16 times the converter clock). If you choose to stall the processor for 3 clocks to ensure some headroom around the sampling event, then this will consume almost 20% of the processing power of the chip.

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