Today’s mainstream down-conversion reception methods are mainly intermediate frequency reception technologies, which are specifically: first convert the radio frequency signal into an intermediate frequency signal, and then convert it into a baseband signal for processing. Direct sampling of RF signals is technically difficult and uneconomical. In the current transformation research, most applications are to first transform the RF signal to the intermediate frequency, then digitize the analog signal, and then use digital down-conversion technology and multi-rate signal processing technology to perform subsequent processing of the signal.

Today’s mainstream down-conversion reception methods are mainly intermediate frequency reception technologies, which are specifically: first convert the radio frequency signal into an intermediate frequency signal, and then convert it into a baseband signal for processing. Direct sampling of RF signals is technically difficult and uneconomical. In the current transformation research, most applications are to first transform the RF signal to the intermediate frequency, then digitize the analog signal, and then use digital down-conversion technology and multi-rate signal processing technology to perform subsequent processing of the signal.

1. Theoretical analysis of orthogonal architecture

A block diagram of the quadrature ADC architecture is shown in Figure 1.

  Design and Problem Solving of Broadband Orthogonal Architectures in the Analog Domain

First, the RF input signal is a real number, which is expressed as follows:

Design and Problem Solving of Broadband Orthogonal Architectures in the Analog Domain

If both outputs are digitized, the input bandwidth can be doubled, which can be explained from the time or frequency domain: in the time domain, if the sampling frequency is fs, when the input frequency is reached, it must be able to Two sampling samples are obtained in one cycle to meet the Nyquist sampling rate, then the input frequency is fs/2, if there is a Q channel, more than two samples will be collected, so the input frequency can be extended to fs. From the frequency domain, if the input is a real number, the output has positive frequency components and negative frequency components, then the non-ambiguous frequency is fs/2; for complex numbers, because there are no negative frequency components, the input frequency can be extended to fs . However, when the frequency converter covers a wider bandwidth, the I channel and the Q channel may appear unbalanced, the outputs of the two channels may have different amplitudes, and their relative phases may differ by exactly 90°. This unbalance may It will cause the channel to generate an image signal, and its theoretical analysis is as follows: where s

Design and Problem Solving of Broadband Orthogonal Architectures in the Analog Domain

It can be seen from Figure 2 that when the phase imbalance is less than 2°, if the amplitude balance is less than 0.15 dB, the image amplitude will be 35 dB smaller than the expected signal; if the amplitude imbalance is 1.5 dB, the phase imbalance is low. At 20°, the image will be 15 dB smaller than the desired signal amplitude.

In this design, the SRQ-2116 quadrature mixing demodulator is selected, and the Agilent VNA E5071C network analyzer is used to test the phase imbalance. Figure 3 shows the results of testing with the SRQ-2116 evaluation board. It can be seen from Figure 3 that the phase imbalance is much less than 2° in the range of 1 943 to 1964 MHz.

RF is a 25

In this case the image rejection is up to 35 dB.

2. Suppression of local oscillator leakage

The HyperLynx principle circuit for LO leakage zeroing is shown in Figure 5. The resistance value of R28 and R31 is 8 kΩ. In order to make the quadrature coupling of the baseband signal, the bypass capacitors C24 and C30 can be increased. Connect the 1, 2 of S6 to connect the voltage source to the IBIAS, adjust the IBIAS voltage from zero up, and observe whether the LO leakage increases or decreases. If it decreases, the polarity of the IBIAS bias is correct; if it increases, adjust the IBIAS bias negatively, or change the S6 connection to 2,3. Adjust QBIAS in the same way, optimize IBIAS, QBIAS, so that the leakage of LO tends to zero.

The LO leakage at the RF port can be zero-adjusted by introducing a DC bias at the I/Q port, so that the leakage level is lower than –80 dBm. But it will cause the impedance mismatch of the IF interface at the I/Q end and make the performance worse. Therefore, the I/Q port and the ADC drive circuit must be matched. If not matched, the second harmonic of the LO will leak to the I/Q output port of the demodulator, this leakage will cancel the effect of the LO zeroing, and the residual DC component generated by the LO signal reflection at the I/Q IF port Affects the zero adjustment state.

The simulation of the IF filter is shown in Figure 6. The IF low-pass filter can remove unnecessary high-frequency components in the signal, reduce the sampling frequency, avoid frequency confusion, and remove high-frequency interference. This design uses ADS simulation software to design and simulate the filter. To better observe the higher frequency results, the frequency range of the simulation has been specifically increased. It can be seen from the simulation results that the filter can better meet the actual requirements in the radio frequency range.

The RLC filter circuit is shown in Figure 7. Choose the resistance value of 50Ω and choose the appropriate capacitor C according to the corner frequency 1/(2RC), so that the fLO and 2fLO clutter can be fully filtered, and the flatness of the frequency response characteristics at the baseband frequency will not be affected; for I+/I- And the common-mode fLO and 2fLO signals at one end of Q+/Q, the RC network is equivalent to a 25Ω termination resistor. The RC network provides an absorption path for fLO and 2fLO leakage; the Inductor provides a high impedance path to suppress reverse radiation. Through the measurement, it can be seen that the suppression of fLO and 2fLO leakage can reach 8 dB and 14.5 dB, respectively.

3. Conclusion

Some key technologies in the design and implementation of broadband orthogonal architecture in the analog domain and some technical difficulties encountered in practical design are studied and demonstrated, and corresponding solutions are proposed creatively. Through simulation and actual testing with network analyzer, it can be concluded that the design method in this paper fully meets the requirements of the system and has certain reference significance.

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