“MAX195 is a 16-bit successive approximation ADC. It combines high-precision, high-speed, low power consumption (consumption current of only 10μA) shutdown mode and other performances. The internal calibration circuit corrects linearity and offset errors, so all rated performance indicators can be achieved without external adjustments.
Author: Wang Xiaoguang
MAX195 is a 16-bit successive approximation ADC. It combines high-precision, high-speed, low power consumption (consumption current of only 10μA) shutdown mode and other performances. The internal calibration circuit corrects linearity and offset errors, so all rated performance indicators can be achieved without external adjustments. The capacitive DAC structure makes it have a unique 85kbps tracking/holding function, and the conversion time is only 9.4μs. Three-state serial data output and pin-selectable unipolar (0～VREF) or bipolar (-VREF～＋VREF) input range make it widely used in portable instruments, medical signal acquisition and multi-sensor measurement, etc. In the system.
1 MAX195 pin and description
MAX195 has 16 pins, its arrangement is shown as in Fig. 1.
2 MAX195 conversion principle and timing
The MAX195 chip contains a capacitive digital-to-analog converter (DAC), which can track and hold the analog input, and then successively approach the register and the comparator, and under the control of the conversion clock CLK, the analog input is converted into 16 bits The digital code is output through the on-chip serial interface. The interface and control logic in the chip are easily connected to most microprocessors, reducing the need for external components.
The sequence of its conversion and data output is shown in Figure 2.
It can be seen from the timing sequence that after at least three or more clock cycles have elapsed after the previous conversion ends, the conversion starts on the falling edge of the valid CLK clock (4 CLK cycles are required for MAX195 to track/hold and collect signals). At the same time, the falling edge of the next clock goes high, after 9.4μs (CLK is 1. 7MHz) after the conversion is over, it changes from high to low, and the conversion end signal is given, which can be sent to interrupt or be queried. The end of the conversion is output from the DOUT end of the three-state serial port. During the conversion, the data is controlled by CLK, and the data can also be read out by the SCLK serial clock between two conversions. The highest rate can reach 5Mbps. The situation shown in Figure 2 is the latter. After keeping the low level, at the falling edge of each SCLK, the DOUT terminal outputs one bit of data in the order of MSB first, otherwise, DOUT is in a high impedance state.
3 Calibration of MAX195
The MAX195 is automatically calibrated when it is powered on. In order to reduce the influence of noise, each calibration test is performed multiple times and the results are averaged. At a clock frequency of 1.7MHz, calibration requires approximately 14000 clock cycles or 8.2ms. In addition to power-on calibration, pulling to a low level will cause the MAX195 to suspend work, so that it will start a new calibration when it returns to the high level again.
Note: It is only recommended to re-calibrate during the power-on delay period when the power supply has not stabilized before the power-on calibration or the power supply voltage, ambient temperature, and clock frequency have changed significantly.
The software calibration reference subroutine is as follows:
4 AT89C51 and MAX195 interface design
Fig. 3 is the hardware circuit diagram of AT89C51 and MAX195 interface.
In the picture, the ALE end output signal of AT89C51 (equal to 1/6 crystal frequency fosc=6MHz) is used as the CLK conversion clock. P1.5 is used as the starting control terminal of MAX195. If the terminal is left open, it means that the analog signal can be inputted bipolar, or it can be connected to +5V-unipolar input as required; grounding-closed mode.
According to Figure 3, the A/D sampling procedure is given as follows:
Note: The sampling results are stored in R2 and R33.