“For R&D personnel, everyone is always in pursuit of low-power designs. The use of low-power design can undoubtedly bring many benefits. In order to help you understand how to reduce power consumption, in this article, Xiaobian will explain the design techniques for reducing FPGA power consumption.
For R&D personnel, everyone is always in pursuit of low-power designs. The use of low-power design can undoubtedly bring many benefits. To help you understand how to reduce power consumption, in this article, I will describe design techniques for reducing power consumption in FPGAs.
Next-generation FPGAs are getting faster, denser, and more logic resources. So how can you ensure that power consumption doesn’t increase with these? Many design choices can affect the power consumption of a system, ranging from obvious device choices to subtle choices of state machine values based on frequency of use.
To better understand why the design techniques discussed in this article can save power, let’s start with a brief introduction to power consumption.
Power consumption consists of two factors: dynamic power and static power. Dynamic power is the power required to charge and discharge capacitive loads within the device. It largely depends on frequency, voltage and load. Each of these three variables is under some of your control.
Dynamic Power = Capacitance × Voltage 2 × Frequency
Quiescent power is the power dissipation caused by the leakage currents (source-to-drain and gate leakage, often concentrated as quiescent currents) of all transistors in the device, plus any other constant power requirements. Leakage current strongly depends on junction temperature and Transistor size.
Constant power requirements include current leakage due to terminations such as pull-up resistors. There are not many measures that can be taken to affect leakage, but constant power consumption can be controlled.
Consider power consumption early
The power decisions you make in the early stages of your design have the biggest impact. Deciding what components to use has a significant impact on power consumption, while inserting a BUFGMUX on the clock has little effect. The earlier the consideration of power consumption, the better.
Not all components have the same quiescent power dissipation. As a general rule, the smaller the device process technology size, the greater the leakage power dissipation. But not all process technologies are created equal. For example, for 90 nm technology, there is a significant difference in quiescent power consumption between Virtex-4 devices and other 90 nm FPGA technologies,
However, while static power consumption increases as process technology shrinks, dynamic power consumption decreases due to the lower voltage and capacitance of the smaller process. Consider which power consumption affects your design more – standby (quiescent) power or dynamic power.
All Xilinx devices have specialized logic except for the general purpose slice logic unit. It comes in the form of block RAM, 18×18 multipliers, DSP48 blocks, SRL16s, and other logic. This is not only because specialized logic has higher performance, but also because they have lower density and thus can consume less power for the same operation. When evaluating your device options, consider the type and amount of specialized logic.
Selecting the appropriate I/O standard can also save power. These are simple decisions like choosing the lowest drive strength or lower voltage standard. When system speed requires the use of high-power I/O standards, plan a default state to reduce power consumption. Some I/O standards (eg GTL/+) require a pull-up resistor to function properly. Therefore, if the default state of the I/O is high instead of low, the DC power consumption through the termination resistor can be saved. For GTL+, a proper default setting of 1.5V for a 50Ω termination resistor results in a power savings of 30 mA per I/O.
When the data on the bus is related to the register, chip select or clock enable logic is often used to control the enable of the register. Going a step further, “data-enable” this logic as early as possible to prevent unnecessary transitions between the data bus and the clock-enable register combinational logic, as shown in Figure 1. The red waveform represents the original design; the green waveform represents the modified design.
Another option is to do this “data enable” on the board rather than on the chip. to minimize processor clock cycles. The concept is to use the CPLD to offload simple tasks from the processor so that it can stay in standby mode longer.
Let’s look at a state machine with frequent state transitions between state 7 and state 8. If you choose binary encoding for this state machine, it will mean that for each state transition between state 7 and state 8, four bits will need to change state, as shown in Table 1. If the state machine were designed in Gray code instead of binary, the number of logic transitions required to transition between these two states would be reduced to just one bit. Alternatively, the same effect can be achieved if states 7 and 8 are encoded as 0010 and 0011, respectively.
Of all the power-absorbing signals in a design, the clock is the culprit. While a clock may run at 100 MHz, signals derived from that clock typically run at a smaller fraction (typically 12% to 15%) of the master clock frequency. In addition, the fan-out of the clock is generally high – two factors that show that the clock should be carefully studied in order to reduce power consumption.
If a portion of the design can be inactive, consider using a BUFG-MUX to disable clock tree flips instead of clock enables. The clock enable will prevent unnecessary flipping of the registers, but the clock tree will still flip, consuming power. But using a clock enable is better than nothing.
Isolate clocks to use a minimum number of signal regions. Unused clock tree signal regions do not toggle, reducing the load on that clock network. Careful layout can achieve this without affecting the actual design.
The same concept can obviously be used for FPGAs as well. Although the FPGA does not necessarily have a standby mode, using a CPLD to intercept bus data midway and selectively feed the data to the FPGA can also eliminate unnecessary input transitions.
CoolRunner-II CPLDs include a feature called “data gating” that inhibits logic transitions on pins from reaching the CPLD’s internal logic. This data gating enable can be controlled by an on-chip logic OR pin.
State Machine Design
The state machine is enumerated according to the predicted next state condition, and the state value with few transition bits between normal states is selected. In this way, you can minimize the amount of transitions (frequency) of the state machine network. Determining normal transitions and selecting appropriate state values is an easy way to reduce power consumption with little impact on the design. The simpler the encoding form (one-bit efficient encoding or Gray code), the less decoding logic is used.
Power Estimation Tool
Xilinx provides two forms of power estimation tools: a pre-design tool called Web Power Tools and a post-design tool called Xpower. With it, you can get power estimates based on design utilization estimates without the need for actual design files.
XPower is a post-design tool that analyzes actual device utilization and combines actual post-fit simulation data (VCD file format) to give actual power consumption data. With Xpower, you can analyze the impact of design changes on total power consumption without touching the chip at all.
Web-Based Power Tool
Web-based power estimation is the quickest and easiest way to get a device power profile early in the design flow. New versions of these tools are released every quarter, so the information is always up-to-date and no installation or download is required, just an internet connection and a web browser. You can specify design parameters and save and load design settings without the hassle of re-entering design parameters through interactive use. Get started as soon as you have an estimate of the design behavior and select the target device.
Xpower: Integrated Design-Specific Power Analysis
Xpower is a free component of all Xilinx ISE design tools that allows you to make much more detailed estimates of your design-based power requirements. XPower estimates device power consumption based on a map or post-place-and-route design.
For mature production FPGAs and CPLDs, XPower computes power estimates with an average design suite error of less than 10%. It combines device data with your design files and provides a high-accuracy report estimating device power consumption based on your specific design information.
Integrated directly into the ISE software, XPower provides a detailed hierarchical power Display, detailed summary reports, and power wizards, making it easy for even novice users to get started. XPower accepts simulated design activity data and can run in GUI mode and batch mode.
XPower will consider every net and logic element in the design. ISE design files provide accurate resource usage; XPower cross-reference routing information and characterizing capacitance data. The physical resource is then characterized for capacitance. Design characterization will continue on new devices to give the most accurate results. Xpower uses the network rollover rate and output load. XPower then calculates power dissipation and junction temperature, and can also Display power consumption data for individual nets.