The author (Takashi Yugami, the author of this article) became a semiconductor technician when Japan swept the world with DRAM (16 years until 2002). Since then, I don’t think semiconductors have gotten as much attention from the world as they are today. This brings up a well-worn question – when will Moore’s Law come to an end? When will the shrinking of “and” semiconductors stop?
From the second half of the 1980s to the mid-1990s, further scaling of semiconductors was considered impossible due to severe charging damage caused by processes using plasma, such as dry etching. However, Japanese technicians carried out pioneering research. After that, Japan and the United States conducted thorough research, and as a result, plasma dry etching has continued to be used until now. Therefore, in this regard, semiconductor scaling will not stop.
After that, I remember starting to talk again about “Has semiconductor scaling reached its limit?” when ArF exposure equipment reached its resolution limit in 2006 (Figure 1). At that time, the author was a teacher of business management at Doshisha University. I accepted a research commission from a semiconductor-related company, and said to the key figures related to the most advanced refinement at that time: “How many nanometers do you think the refinement limit of semiconductors is?” Such listening to the investigation.
Figure 1. Principle and history of lithography
It is interesting to revisit the findings now. Therefore, this article is about “When will the scaling of semiconductors stop?” and “When will Moore’s Law come to an end?”
Miniature survey conducted in 2007
Around 2006, the scaling of logic device semiconductors is developing from 65nm to 45nm. However, the state-of-the-art exposure equipment at the time, ArF (now called ArF dry method), had reached its resolution limit, and EUV (Extreme Ultraviolet), a candidate for the next-generation exposure equipment, was piling up, and even R&D equipment did not exist. Therefore, “Isn’t the miniaturization of semiconductors over?” This atmosphere is floating in the semiconductor industry.
The author, who was a business teacher at Doshisha University at the time, asked, “When will the miniaturization of semiconductors stop?” Influenced by this commissioned research, I traveled around the world from July to September 2007 (two full months), visiting cutting-edge semiconductor manufacturers, Manufacturers of manufacturing equipment and materials, the US-based consortium SEMATECH and Europe’s imec, surveyed key players associated with miniaturization.
When asked at the time, we looked at logic devices and memory separately. Questions include e.g. what do you think the half-pitch (hp) would be in a few nm bound”. Looking back at the time, the pitch of the finest metal wiring (M1) was roughly proportional to the technology node, so the above question was “the hp bound for M1” How many nm? “(figure 2).
Figure 2. Progress and future forecasts of semiconductor scaling Source: Toshiro Hiramoto (Institute of Production Technology, University of Tokyo)
In addition, with regard to memory, NAND-type flash memory continues to undergo two-dimensional scaling, and its level is more advanced than DRAM, so the question asked is “How many nm do you think the hp of the micro-wiring M1 (or gate length) of NAND flash memory is?” . Figure 3 shows the results of this investigation. A, B…, Z represent the serial numbers of the technicians who answered the author’s question (the survey was conducted in the order of A→B→…,Z).
Figure 3. “What is the miniature limit?” (hp, nm) at the time of the 2007 survey
The limits of miniaturization are easily broken
From the results, many technicians believed that the hp on logic devices was the limit when the hp was 45nm, and the memory was the limit when the hp was 32nm. The boundaries of this miniaturization are simply broken by techniques such as ArF dipping and SADP (Self-Arigned Double Patterning, ) by extending the ArF dry process. Even if there were quite a few technicians at that time that “exposure equipment as complicated as immersion cannot be activated”, “even if the SADP is miniaturized, the yield will not be improved”.
It is worth mentioning that when visiting TSMC to investigate, I contacted TSMC friends and asked them to gather 5~6 executive-level people. The author projected previous listening findings (A to X) on a slide in the TSMC conference room in Hsinchu, Taiwan.
All the TSMC-related people who gathered at that time laughed out loud. And, “what are you talking about, hp45nm and hp32nm is the limit or something like that? We’ve already developed 22nm?”. 2 of them also answered my question, and the answers they gave were hp16nm and hp10nm.
I think TSMC’s 7nm M1 mass-produced from 2018 is around hp18nm, and the most advanced 5nm M1 mass-produced in 2020 is around hp16nm. Therefore, TSMC’s limit statement at the time was broken in 2020. As for the remaining hp 10nm, I think it is close to its limit in TSMC’s 3nm, the future 2nm, if the next 1.5nm ~ 1nm is realized, this limit will be broken.
Survey on EUV
It can be seen from the survey of “How many nm is the hp of the miniaturization limit”, in 2007, the extremely difficult EUV was being developed. “For such a problem, they gave the results shown in Figure 4.
Figure 4. Results of the 2007 survey “Is mass production of EUV impossible?”
Here, FIG. 4 is divided into two parts, which are lithography technicians of semiconductor manufacturers, technicians of lithography-related manufacturing equipment or material manufacturers, and technicians other than lithography. Or it is divided into integration technicians of semiconductor manufacturers and personnel related to manufacturing equipment or materials other than lithography.
Therefore, among the 18 lithography-related personnel, more than half of the 10 people answered “Yes (that is, EUV mass production machine cannot be carried out)” (Figure 4-1). On the other hand, 7 out of 10 people involved except lithography answered “NO (that is, EUV mass production machines can)” (Figure 4-2). This comparison is really interesting.
Lithography-related personnel probably feel that “the mass production machine cannot be realized” because they are very familiar with the difficulties of EUV development. However, the relevant personnel other than lithography did not trust lithography experts from the beginning, thinking that “lithography experts always say that they can’t do it and make trouble.”
And judging from the results, in 2019, TSMC used EUV lithography machines in large numbers at 7nm+, and in 2020, the 5nm of EUV is also suitable for wiring. So, it turns out that what the lithography experts said was incorrect. That said, don’t believe that lithography experts “can’t do it” are better.
In this way, in the history of the semiconductor industry, the limit of miniaturization has always been broken. Although the pace has slowed down, it has not stopped. So what are the prospects for the future?
Regarding miniaturization, it can be seen from the International Technology Roadmap for Semiconductors (ITRS) in 2001. If you continue to move forward according to this roadmap, the most cutting-edge is the US Intel that mass-produces PC processors, so this roadmap is also called “Intel Technology Roadmap for semiconductor” (Intel’s roadmap).
However, after Intel’s 10nm failed in 2016, ITRS also ended that year, and was succeeded by the International Roadmap for Devices and Systems (IRDS), but no one said it was “Intel’s roadmap” anymore. In addition, it is TSMC that has jumped to the forefront of miniaturization instead of Intel. Compared with IRDS, the roadmap of semiconductors feels that what the European consortium imec has published is closer to reality.
Evolution and Miniaturization of Logic Device CMOS
Figure 5 shows the actual results and predictions of CMOS evolution and refinement from 1990 to 2030. Through this picture, you can see the refined past, present and future at a glance. For me it is a moving picture.
Figure 5. Technology evolution of logic device CMOS
The scaling down of scaling rules advocated by IBM’s Robert H. Dennard did not progress well until the mid-2000s. That is to say, a 70% shrinkage has been achieved within 2 years, improving the working speed of transistors, reducing power consumption and integration. However, starting around 2003, the scaling of gate lengths has slowed down. From this point on, the operating speed of the transistors cannot be increased even if they are scaled down. Therefore, as auxiliary technologies, the industry has begun to introduce Cu/Low-k wiring, strained silicon (Strain Si), High-k/Metal gates, FinFETs, and the like.
In addition, the calibration of the thinnest wiring (M1) in which “Dense Metal Pichi” is written in Fig. 5 may be continued while decelerating.
And, after Intel’s 10nm failure in 2016, the protagonist of miniaturization shifted to TSMC. In this figure, we try to write the technology nodes that TSMC is expected to mass-produce after 2018 and in the future.
Comparing imec’s roadmap and TSMC’s mass production schedule, it can be seen that although the applicable period of EUV is the same, the period of Nanosheets using Gate All Arround (GAA) structure in CMOS is different. imec envisages 3nm, but TSMC, which is currently in the risk trial production of this node, still uses the FinFET process, and they plan to use Nanosheets from 2nm.
In any case, the shrinking of gate lengths and micro-wiring M1 will not stop until 2030. According to this graph, there will not even be a slowdown in the next 10 years. On the contrary, if a new CMOS structure called 2D channels is adopted at 1nm, the scaling of the gate length will be greatly improved.
Scaling of transistors and fine wiring
FIG. 6 shows the transition of Transistor structure accompanying the scaling of logic devices.
As shown, from 3nm to 2nm, transistors change from FinFETs to Nanosheets. In addition, imec believes that from 2nm to 1.5nm, the Forksheets that separate nMOS and pMOS are promising. In contrast, in TSMC’s mass production plan, Nanosheets is used at 2nm, but Forksheets has not been heard.
Figure 6. Roadmap for logic device scaling (transistors)
In addition, imec envisages the formation of nMOS and pMOS Compulementary FETs (CFETs) in the vertical direction near 1.5nm, but this has not seen any clues in TSMC’s R&D roadmap. However, TSMC is also carrying out the same research and development for 2D atomic channels that are expected to appear at 1nm and later.
As such, there are all kinds of options for transistors, and it feels like it’s really about to evolve. However, the development of fine wiring is quite serious. In the currently mainstream Cu wiring, when the wiring width is refined, the scattering due to the grayscale of Cu and the increase in resistance due to the scattering of the barrier metal become big problems ( FIG. 7 ).
Figure 7. Roadmap for micro-routing miniaturization
The current Cu Dual Damascene can only be used up to 3nm. Starting from 2nm, Ru is used for the Hybrid of VIA, and Ru is directly processed (Subtractive) at 1.5nm, and then it is necessary to make the interlayer insulating film Air Gap. Furthermore, 1nm and beyond requires the exploration of completely new materials.
In summary, there are various candidates for transistor structures by 2030, but with the refinement of wiring, the problem of increased resistance is unavoidable. If mass production is to be carried out, it is necessary to change materials for this. Quite a bold development.
EUV miniature roadmap
As mentioned above, between now and 2030, the structure of transistors will be changed, and the formation methods and materials of fine wiring will continue to be scaled. What will happen to EUV as necessary for this?
Figure 8 shows the EUV miniaturization roadmap. In the current state-of-the-art miniaturization, EUV (hereinafter referred to as ReglarNA) with a lens aperture number NA=0.33 is used. Thereafter, for finer refinement, EUV scaling (with a slight deviation from the numbering in Figure 8) is implemented in the roadmap for the next four stages.
Figure 8. Roadmap for EUV lithography scaling
The microfabrication of 1.28-32nm pitch is the limit of ReglarNA EUV single exposure.
2. In the case of 22-24nm pitch, perform SADP under EUV of ReglarNA
3. After 18nm pitch, use EUV with NA=0.55 (called HighNA)
4. For further fine processing, use High NA+SADP
The above shows the EUV miniature roadmap until 2030. The problem is that the EUV value of ReglarNA is 16 to 18 billion yen, while the EUV value of High NA, which will debut around 2024, will reach 48 billion yen. In the end, is logic semiconductor manufactured using such expensive exposure equipment established as a business? Wafer cost is another consideration when using HighNA EUV.
It is said that HighNA’s EUV debut is around 2024. In terms of TSMC’s technology node, it is about 2nm. The idea is the same as imec. On the premise of applying the High NA EUV lithography machine to the 2nm+ generation, let’s calculate the cost of the chip (Figure 9).
Figure 9. Wafer cost when using HighNA EUV
In this calculation, it is assumed that (1) HighNA’s EUV equipment price is 1.5 times that of ReglarNA’s EUV, and (2) the throughput is unchanged. Therefore, if the EUV value of ReglarNA is 18 billion yen, the EUV value of HighNA must be 27 billion yen (if the rumored 48 billion yen, the following calculation is not valid).
Under this assumption, in the chip manufacturing process, there are Front End of Line (FEOL) for forming transistors, Middle of Line (MOL) for connecting channels between transistors and wiring, and Back End of Line (MOL) for forming multilayer wiring. BEOL) and other three processes.
In the 2nm+ technology node, regarding whether to use EUV with High NA, and how much to use, we compare the chip cost in three cases.
1. The chip cost when EUV of Regular NA is applied to 14 layers and ArF immersion applied to 2 layers is set to “1”. There may be many EUF+SADP processes of ReglarNA. 2. As the solution adopted in the early stage, if the EUV of High NA is 4 layers, the EUV of Regular NA is 6 layers, and the ArF immersion type is 2 layers, the chip cost can be reduced by 5%. 3. If all are replaced with EUV of High NA, the cost can be reduced by 14%.
That means that even with a very expensive EUV lithography machine with High NA, chip costs can be cut (but two assumptions must be met). And it can be seen from Figure 9 that the cost of FEOL is almost unchanged, but the processing cost of MOL and BEOL can be greatly reduced. Therefore, if the EUV value of HighNA is less than 30 billion yen per unit, not only can it be scaled, but also the cost of the chip can be reduced, so I can only ask ASML to do my best.
The Era of the Triwizard Hegemony Begins
From now on, the R&D that fabs invest in each year will become more difficult and expensive, but the scaling shows no signs of stopping. Now, TSMC is leading the way in miniaturization, but Intel, under the leadership of Mr. Pat Gelsinger, is expected to catch up around 2nm. But Intel recently changed the name of its technology node, officially calling it “Intel 20A”
Figure 10. Names of Intel technology nodes
In this case, in the future, with Samsung and Intel as the center, Samsung and Intel will be the center, and the competition for miniaturization of the three parties may intensify. Even so, why does the outsourced factory TSMC continue to shrink like this?
As I said in my previous article, 10 years ago, the miniature felt like a speeding 200 kilometers per hour on the high speed of Europe. After that, the refined deceleration is a fact, but even so, TSMC is still speeding on the field trail at a speed of 100km per hour. The width of the field trail narrows every year, and the car will fall into the field if you drive the wrong way. Dangerous. However, they continued to run at a speed of 100 kilometers per hour.
Why does TSMC as a production factory have to run on the field trail at a speed of 100Km per hour? In fact, I don’t think the production plant TSMC has a roadmap (arguably meaningless). TSMC is always outsourced, so it can only be manufactured by TSMC according to the requirements of the consignor.
So, who would make TSMC “run on a field trail at a speed of 100km/h”? That is Apple of America. TSMC desperately responded after Apple asked for a “seemingly impossible miniature”.
Is Apple the biggest mover in the chip industry?
Figure 11 shows the number of smartphone shipments by company per quarter. After 2012, the number one shipment is probably Samsung. In addition, around 2012, China’s Huawei started an amazing growth. In the second quarter (Q2) of 2020, it surpassed Samsung and became the world’s No. 1. However, due to US sanctions, after September 15, 2020, due to TSMC and other places purchased semiconductors, and Huawei quickly stalled after that.
Figure 11. Quarterly smartphone shipments by company (~2021Q2)
And Apple’s most characteristic shipping habit is to reach the top in the fourth quarter (Q4) of each year. In particular, in the Q4 quarter of 2020, shipments reached an all-time high of 90 million units. That’s the beauty of the American Christmas business war.
Apple releases new iPhones around July every year, and in the December Christmas business war, the goal is to mass-produce a total of about 100 million units (the actual assembly is Taiwan’s Hon Hai, which has a large factory group in China). Figure 12 shows Apple’s new iPhones and the application processor (AP) nodes installed on them from 2019 to 2023, as well as statistics on whether their chips use EUV on that technology node.
Figure 12. The presence or absence of iPhone’s AP, Technology Node, and EUV applications
To catch up with this plan, TSMC must ramp up the process of the improved N5P at 5nm (N5) by 2021 at the latest and manufacture 100 million iPhone APs in Q3. At the same time, in order to mass-produce the N4 (an improved version of the N5 family) scheduled for mass production in 2022, they must complete the research and development within this year and have to start risk production. That means they don’t seem to be able to keep up with 3nm.
Every year TSMC has to continue research and development and mass production for Apple. Because, as shown in Figure 13, TSMC’s sales of apples reach 25%, and apples are TSMC’s largest customer.
Figure 13. Share of TSMC Sales (2020)
Moore’s Law is the “Law of Human Desire”
Let’s calculate how difficult it is to make 100 million APs in state-of-the-art logic devices. The A13 chip made for the iPhone 11 in 2019 measures 98.48mm2. Calculated from 12-inch wafers, it is 707, and if the yield is set to 90% (I don’t think it is too high), it is 636.
In this case, to manufacture 100 million wafers, about 1.5 million wafers must be invested. The A13 is manufactured using 7nm (N7) without EUV. It is said that the monthly production capacity of N7 is about 150K (150,000 sheets) of 12-inch wafers. As a result, TSMC had to fully operate the N7 production line within 10 months for the A13. During this period, AMD’s CPU, NVIDIA’s GPU, MediaTek’s AP, and Qualcomm’s baseband chips have no chance to enter.
Therefore, the most advanced logic devices are almost monopolized by Apple’s AP every year, and after the commotion is over, other cutting-edge products of FABLESS have to be manufactured.
Conversely, TSMC’s largest customer, Apple, requests the manufacture of APs in state-of-the-art processes every year, so TSMC developed this logic device, other fabless fabs due to its state-of-the-art process (albeit a bit late) Can get its boon, which means producing cutting-edge chips.
Judging from this situation, it can be said that the reason why TSMC can continue to be the most advanced in the world is because of the Christmas business war in the United States. That is, how many new iPhones Apple sells each December, or whether Americans are willing to buy the new iPhones. In other words, TSMC’s energetic driving force for “running on a field trail at a speed of 100km/h” is the reason Americans want to buy an iPhone with “higher performance, easier use and more durable battery”.
In short, the advancement of TSMC can see that Moore’s Law is the law of human desire. (More precisely, American desire?).
Moore’s Law Won’t End Even If Scaling Stops
Even after explaining the above, many people retorted: “If the refinement becomes the atomic level, the scaling will stop.” However, even so, the author insists: “Even if the refinement becomes the atomic level, stop Moore’s Law will continue.”.
At the 2019 VLSI Symposium, Mr. Robert D. Clark (Tokyo Electron Technology Center) gave a speech entitled “Selective and Self-Limited Thein Film Process for the Atomic Scale Era”. Although he doesn’t have any profile on Sunday Workshop. However, I was deeply moved by a slide by Robert D. Clark.
Figure 14. The vertical axis is the calculation speed, and Moore’s Law has lasted for 120 years
The “Moore’s Law” advocated by Mr. Gordon E. Moore, one of the founders of Intel, is explained as the integration of transistors has doubled in 2 years. However, Mr. Robert D. Clark explained in Fig. 14 that if the vertical axis is not the integration of transistors, but the speed of the computer, then “Moore’s Law lasted for 120 years from 1900 to the present”.
The technology nodes of 7nm, 5nm, and 3nm mentioned by TSMC before are just trade names, and their dimensions cannot be found anywhere on the chip. On the contrary, with the development of the times, performance such as power drop and high speed increase, transistor size (or footprint) shrinks, and chip size becomes smaller. That is, Power, Performance, and Area (PPA) are improved.
So even if the scaling stops, Moore’s Law will not end as long as one of the PPAs is advancing.
So, to wrap up this long thread. First, scaling cannot be stopped until at least 2030. This is basically the same as “hp10nm is the limit” predicted by a TSMC executive in 2007. Also, because lithography experts are always pessimistic, what they say is less credible. The proof is that the “absolutely impossible mass production” EUV lithography machine manufacturing has been achieved.
Moreover, now TSMC is frantically shrinking, so the driving force behind Moore’s Law is nothing else, but “human desire”. Therefore, as long as human beings continue to maintain their desires, they will not stop refining for the time being. And, even if scaling stops at the atomic level, if parameters other than the integration of transistors (such as the speed of a computer) are taken as the vertical axis, Moore’s Law may continue until the end of mankind.
Therefore, from the current point of view, the biggest issue of semiconductor scaling and Moore’s Law is to defeat the new coronavirus that mutates into delta.