“Infineon’s 1ED44173/5/6 are new low-side gate driver ICs with integrated overcurrent protection (OCP), fault status output and enable functions. This highly integrated driver is very friendly for PFC (Digitally Controlled Power Factor Correction) applications with boost topology and ground reference.

“

Author: Wchu1, Translator: Chen Ziying

Infineon’s 1ED44173/5/6 are new low-side gate driver ICs with integrated overcurrent protection (OCP), fault status output and enable functions. This highly integrated driver is very friendly for PFC (Digitally Controlled Power Factor Correction) applications with boost topology and ground reference.

In PFC applications, shunts are used to sample power switch current or DC bus current. The location of the diverter varies depending on the control method selected. For example, in Example 1 of Figure 1, a shunt is placed between the IGBT emitter and system ground to sample the current of the power switch when the controller implements peak current control or current balance control in an interleaved PFC application.

In contrast, Figure 1, Example 2 shows a shunt between system ground and the negative side of the DC bus to sense the DC bus current. This configuration is often used for average current mode control, where the digital controller can calculate the input power based on the average current and DC bus voltage feedback.

Figure 1: Two different types of low-side gate drivers with OCP: 1ED44176N01F (Example 1) has positive current sampling to meet the requirements of the first shunt position, while 1ED44173/5N01B (Example 2) has negative current sensing to Meets requirements for second shunt location

Application in Home Air Conditioning

In today’s Residential Air Conditioning (RAC) applications with digitally controlled PFC, the controller uses the power feedback signal to achieve adaptive DC bus voltage control. This allows for reduced losses at light loads when using a lower DC bus voltage, and switching to a full DC bus when full load is required.

Due to the different shunt configurations, Infineon has designed two different types of low-side gate drivers with OCP: 1ED44176N01F (Fig. 1, example 1), and 1ED44173N01B and 1ED44175N01B (Fig. 1, example 2). The former has positive current sensing to satisfy the shunt configuration of Example 1, while the latter two have negative current sensing to satisfy the shunt configuration of Example 2. The 1ED44175N01B is aimed at driving IGBTs, while the 1ED44173N01B is aimed at driving MOSFETs.

Figure 2: Differences in functionality of 1ED44173/5/6

In high-current, high-speed switching circuits like PFCs, PCB layout is always a challenge. A good PCB layout ensures device operating conditions and design stability. Improper components or layout can cause switching instability, excessive voltage ringing, or circuit latch-up.

Best PCB Layout Tips for Gate Driver ICs

1. When using an RC filter circuit between the microcontroller and the gate driver, keep the wiring at the input as short as possible (less than 2-3 cm).
2. The EN/FLT output is an open-drain output, so it needs to be pulled up to a 5V or 3.3V logic power supply with a pull-up resistor. When designing, place the RC filter close to the gate driver.
3. To prevent false triggering in overcurrent protection, the RC filter wiring between OCP and ground should be as short as possible.
4. Install each capacitor as close to the gate driver pins as possible.
5. Connect the ground wire of the microcontroller directly to the COM pin (1ED44173/5N01B).
6. Connect the gate output return to COM and connect the microcontroller’s ground pin to the VSS logic ground pin (1ED44176N01F), this prevents noise coupling of the logic input pins to the driver output return.

Let’s take a look at what the right layout can do. The example below shows the circuit (Fig. 3) and layout implementation (Fig. 4) of a 1ED44175N01B and a TO-247 IGBT such as the IKW40N65WR5. With this design, the loop area and inductance of the PCB can be reduced.

Figure 3: Circuit diagram of 1ED44175N01B

Figure 4: PCB layout of the above circuit

How to reduce PCB trace enclosing area to reduce parasitic inductance

・ Place 1ED44175N01B close to IGBT gate and emitter
・Place the decoupling capacitor (C3) directly on the VCC and COM pins
・ Place filter capacitors (C1 and C4) and fault clear time programming capacitor (C2) close to the pins
・ Place the ground plane directly above or below the 1ED44175N01B, which reduces trace inductance

Additionally, the ground plane connected to COM helps act as a radiated noise shield and provides a thermal path for the device to dissipate power. Following these layout tips can eliminate common noise coupling problems and save you development time.