“The anti-information leakage system designed in this paper realizes the simultaneous transmission of multiple pixels by converting the format of the video signal. Figure 1 is a schematic diagram of the conversion principle of video information format. The input data is the digital video signal obtained after the serial analog video signal is converted by A/D. When the system receives the information, the sequence is received by a single pixel. At this time, the data is ” Pixel Pack” format. After being processed by the format conversion module, these received video signal data in “pixel packet” format are converted into output data arranged in “bit plane” format.
Authors: Zhang Yun; Jia Jianyuan; Shao Min
If the Display terminal is a digital micromirror DMD (Digital MicromirrorDevice) display. The monitor stores the image signal of each pixel of the computer in the SDRAM bidirectional buffer after DLP (Digital Light Processing), and when a frame of image is received, the internal data processing circuit simultaneously activates the corresponding microcomputer The mirror movement completes the Display of one frame of image. The peak digital driving voltage of the DMD display does not exceed 33.5V, the electromagnetic radiation is very low, and each micro-lens is driven at the same time, forming an external radiation signal that interferes with each other, and it is extremely difficult to decode, making it a display without information leakage. At this point, the radiation of the video cable dominates the radiation of the entire video channel. If the video signal is processed before it is transmitted through the video cable to the display, electromagnetic radiation and information leakage can be effectively reduced.
1 Video information leakage mechanism and solution
1.1 Leakage mechanism during video information transmission
In the computer video channel, the transmission of information is mainly in two ways: parallel transmission and serial transmission. At present, common video information is serially transmitted. When the wavelength of the serially transmitted signal is comparable to the physical length of the video cable, the video cable acts as an antenna, which is prone to high-intensity electromagnetic leakage of useful information. Time division reception, frequency division reception and azimuth reception are easily implemented for serial signals. So serial video information is easy to be stolen and reproduced.
In the parallel transmission mode, since the interval between the data lines is small and the frequency of the transmitted signal is the same or similar, the interception is much more difficult. However, after converting the R, G, and B serial analog video signals into digital signals, if they are directly transmitted without processing, the information of different bits of a pixel is still transmitted at the same time. Therefore, from the pixel point of view Consider, still serial transmission. If the transmitted image has only two colors of black and white, then the data on the parallel transmission cable at a certain moment is all “1” or all “0”, that is, each signal line in the parallel cable has the same waveform, so there is no need to Each signal line is received separately. At this time, the video cable is similar to the serial transmission method, and the effective information is easily stolen.
1.2 Pixel-based parallel transmission method
In order to effectively reduce the possibility of the video signal being intercepted, a certain format conversion is performed on the video signal before it is sent to the video cable for transmission, so that multiple pixels can be transmitted simultaneously on the parallel cable to achieve true parallelism. That is, pixel-based parallel transmission. In this parallel transmission mode, even if the receiver can receive the radiation information, because the sequence of each pixel cannot be distinguished, the information cannot be reproduced.
The anti-information leakage system designed in this paper realizes the simultaneous transmission of multiple pixels by converting the format of the video signal. Figure 1 is a schematic diagram of the conversion principle of video information format. The input data is the digital video signal obtained after the serial analog video signal is converted by A/D. When the system receives the information, the sequence is received by a single pixel. At this time, the data is ” Pixel Pack” format. After being processed by the format conversion module, these received video signal data in “pixel packet” format are converted into output data arranged in “bit plane” format. At this time, the data of multiple pixels is transmitted on the parallel cable. The video data in the “bit plane” format is transmitted to the display end and then restored to the “pixel packet” format through the format conversion module.
Sequentially received data in the “pixel packet” format can be described in the following aggregated manner: if the system receives n pixels, use D to represent the group of video signals received, and S to represent the sequence of elements in D. The sequence relationship, the number of signal colors is 23m, that is, the three colors of R, G, and B have 2m levels of gray respectively, then:
Similarly, the output data converted to “bit plane” format can also be described in the same way: E represents the data of a frame of image after format conversion, F represents the sequence relationship between elements in E, then:
Converting the video information from the form represented by set D to the form represented by set E is the work to be done by the transmission data format conversion, that is, it is required to output the first binary data of all pixels first, and then output the second binary data of all pixels. Bit binary data until the last bit of binary data for each pixel is finally output. Thus, “bit plane” data is a collection of n pixel points of three colors of data with the same “weight”.
2 System hardware design
2.1 Overall scheme design
According to the principle of parallel transmission of pixels proposed above, an anti-video information leakage system based on FPGA is designed. Figure 2 is a block diagram of the hardware design of the system. The whole system consists of an adapter card at the acquisition end and an adapter card at the display end.
The high-speed video dedicated A/D converter adopts AD’s high-performance AD9883A, the main features are:
(1) Up to 300MHz bandwidth and 140MSPS conversion rate.
(2) Three independent input signal ranges of 0~1.0V are very suitable for sampling video signals.
(3) Provide I2C bus interface, etc. to adapt to a variety of applications.
The high-speed video dedicated D/A converter adopts AD’s high-performance ADV7125, the main features are:
(1) Up to 330M throughput.
(2) Three independent 8-bit DA converters.
(3) TTL compatible input signal, which is convenient for circuit design.
(4) Single power supply 5V or 3.3V power supply, widely used in digital video systems, high-resolution color image display systems.
The working principle of the system is: input the video signal from the graphics card to the acquisition end adapter card, and the A/D converter on the acquisition end adapter card converts the R, G and B analog video signals into three parallel 8-bit signals respectively. The digital signal also performs phase repair and amplitude compensation for the line and field synchronization, making it a standard line and field synchronization signal, and then sends the signal to the FPGA. At the same time, under the control of the state machine, the unit will be pixel The video information is converted to “bit plane” format. After the signal is processed, it is transmitted to the display side adapter card through a parallel transmission cable, and the display side adapter card is responsible for restoring the “bit plane” information to pixel format, and converts the three-channel 24-bit digital video signal through the D/A converter. It is restored to an analog signal and sent to a display device for display.
2.2 Electromagnetic Compatibility Design
2.2.1 Signal Integrity Design
The digital video signal in the system has high requirements for transmission delay. When wiring, the routing paths should be roughly the same and as short as possible to meet the requirements for transmission delay; reasonably arrange the placement of decoupling capacitors, as far as possible Close to the power supply to be decoupled; the wiring of the circuits around the AD9883A chip and the ADV7125 chip should be as short as possible, and the surrounding components should be arranged as compactly as possible to reduce the current loop area and thus reduce electrostatic interference; when placing vias , Be careful not to be too dense, so as not to damage the mirror layer; the resistors, capacitors, inductors and IC chips used in the adapter card are all surface mount components, which are conducive to suppressing electromagnetic interference.
2.2.2 Power Integrity Design
The A/D converter chip and D/A converter chip used in the system have strict requirements on the power supply. In addition to the analog power supply and the digital power supply, the AD9883A also needs a special power supply for the PLL circuit, and the FPGA power supply must have Core power supply and power supply for digital output pins. Therefore, the power design of the whole system is a big problem. Here, two pieces of LT1764 are used as two power supplies for FPGA, two pieces of TPS76333 are used as two power supplies for AD9883A, and one piece of TPS76333 is used as power supply for ADV7125. Both adapter cards adopt a four-layer board structure, the top layer and the bottom layer are used as the signal routing layer, and the middle layer is the ground layer and the power layer respectively, to ensure that the system has a good power supply environment when running at high speed.
3 System logic implementation and simulation
FPGA chip adopts Cyclone series chip EP1C6Q240C8 of Altera Company. Cyclone series chips are based on 1.5V, 0.13μm process, with clock phase-locked loop (PLL) and dedicated DDR interface, supporting a variety of I / O standard chips. Many dedicated hard-core modules are embedded in it and are widely used in programmable system-on-chip (SOPC).
The system processes high-speed image signals with a working clock of nearly 100MHz. In order to obtain better routing effect and system performance, the clock signal must pass through the phase-locked loop to reach the global clock routing network. This design uses Altera’s Maga Wizard to set Cyclone PLL parameters to generate IPcore, which solves the problem of signal delay and also meets the setup and hold time requirements when reading video signals. Figure 3 is the waveform after phase-shifting the input point frequency clock PXCLK_AD using the internal PLL of the FPGA. In the figure, pxclk is the same frequency as the point frequency, and is used as the system reference clock after phase repair and amplitude compensation, and delayclk is the point frequency divided by three frequency, which is used as a delay clock.
3.1 Video information format conversion module
In the acquisition end adapter card, the video information is converted from the “pixel packet” format to the “bit plane” format, which can be completed by an n×m matrix conversion circuit. The input data bus width is m bits, and the output data bus width is n bits. . When the system is working, it needs to continuously input n times each time, that is, read the data of n pixels, and then continuously output m times, that is, write these data to the respective storage locations corresponding to m bit planes. The principle of the format conversion circuit is shown in Figure 4. Using an n×m D flip-flop array, plus the corresponding input and output latch circuits and state machine control circuits, the nxm data format conversion can be realized.
When the i-th pixel is input, the input data state machine triggers the i-th row D flip-flop, and the j-th grayscale information of the i-th pixel is stored in the m-1-j-th D flip-flop in the i-th row (i=1, 2, …, n, j=0, 1, …, m-1), after all n pixels are input, the n×m bits of binary information are all stored in n×m D flip-flops . At this time, the D flip-flop in the i-th row stores the m-bit grayscale information of the i-th pixel, that is, the “pixel packet” format information, and the D-flip-flop in the j-th column stores the m-1th pixel of the n pixel. -j bits of grayscale information, i.e. “bit plane” format information. The output data state machine outputs the data in a certain column of D flip-flops in a certain order, which can realize the output of “bit plane” data. The principle of converting the video information from the “bit plane” format to the “pixel packet” format is similar to that of the above-mentioned matrix circuit, and will not be described here due to space limitations.
When the resolution is 1024×768 and the refresh rate is 75Hz, the point frequency is 78.75MHz. Since the speed of data transmission is inversely proportional to the number of transmission bits, if n
3.2 Synchronization signal delay module
The synchronization signal is a pulse train with a certain frequency, which has a strict synchronization relationship with the video signal, and its frequency is related to the display resolution and screen refresh rate set by the graphics card. In the process of converting the video information format, the video information is delayed by about nine dot frequency periods. In order to keep the mutual timing relationship between the video information and the horizontal and vertical synchronization signals intact when entering the display device, the horizontal and vertical synchronization signals need to be processed by the delay module. Figure 5 is a circuit diagram of the delay circuit of the line synchronization signal in the adapter card of the acquisition end. The system consists of two adapter cards, and the line and field signal delay circuits of the two adapter cards are similar.
3.3 System top-level module
After the entire anti-video information leakage system is designed, its top-level modules are shown in Figure 6 and Figure 7. In the figure, SCI and SDA are used to initialize the AD9883A chip, and DATA_RDY is the custom video information conversion completion signal.
There are format conversion circuits in both adapter cards. After the video information has undergone two format conversions, it is finally restored to the original “pixel packet” format data. Taking the input point frequency PXCLK_AD as 78.75MHz, after using Quartus II for synthesis and timing simulation, the results of the synthesis simulation of the two top-level modules are shown in Figure 8. In the figure, the three sets of data are in the “pixel packet” format, “bit plane” ” format, “pixel pack” format.
It can be seen from Figure 8 that the video information is restored to the original data after two conversions, and the line and field signals also have a certain delay, and maintain good synchronization with the video information, which shows that the pixel-based parallelism The transmission method is feasible.
Under the premise of using DMD display as the terminal display device, the computer anti-video information leakage system based on field programmable gate array (FPGA) and pixel-based parallel transmission mode can realize simultaneous transmission and reception of multiple pixels. It is extremely difficult to distinguish the display order of each pixel from the received radiation information, and the information cannot be reproduced, thereby effectively preventing video information from being intercepted and enhancing information security.