In the actual digital system, a synchronous sequential logic circuit that can be used to store a set of binary codes is usually called a register. Because the flip-flop has a memory function, the flip-flop can be used to easily form a register. Since a flip-flop can store one bit of binary code, the clock ports of n flip-flops can be connected to form a register that stores n bit of binary code. The latch is a level-triggered storage unit. The data storage action depends on the level of the input clock (or enable) signal. As long as the latch is in the enabled state, the output will change with the data input. .

Latches

In the actual digital system, a synchronous sequential logic circuit that can be used to store a set of binary codes is usually called a register. Because the flip-flop has a memory function, the flip-flop can be used to easily form a register. Since a flip-flop can store one bit of binary code, the clock ports of n flip-flops can be connected to form a register that stores n bit of binary code. The latch is a level-triggered storage unit. The data storage action depends on the level of the input clock (or enable) signal. As long as the latch is in the enabled state, the output will change with the data input. .

trigger

The flip-flop is an edge-sensitive storage unit, and the data storage action is synchronized with the rising or falling edge of a certain signal. In the actual digital system, a synchronous sequential logic circuit that can be used to store a set of binary codes is usually called a register. Because the flip-flop has a memory function, the flip-flop can be used to easily form a register. Since a flip-flop can store one bit of binary code, the clock ports of n flip-flops can be connected to form a register that stores n bit of binary code. Some small storage areas where registers are used to store data are used to temporarily store the data involved in operations and the results of operations. In fact, a register is a commonly used sequential logic circuit, but this sequential logic circuit only contains a storage circuit. The storage circuit of the register is composed of latches or flip-flops. Because a latch or flip-flop can store a 1-bit binary number, N latches or flip-flops can form an N-bit register. Flip-flops latch data on the edge of the clock, while latches use level enable to latch data. So the Q output of the flip-flop will be updated every clock edge, and the latch can only be updated when the enable level is active. The flip-flops in some textbooks are actually latches. In FPGA design, it is recommended to use flip-flops instead of latches if it is not necessary.

The clock-controlled D flip-flop is actually a D latch, and the edge D flip-flop is the real D flip-flop. The output of the clock-controlled D flip-flop changes with the input when it is enabled, and the edge flip-flop only changes when the edge changes. The output changes. Two D latches can form a D flip-flop. In the final analysis, dff is edge-triggered and latch is level-triggered. The output of the latch is transparent to the input. What is the input is what the output is. This is the reason why the latch is unstable. The flip-flop is a master-slave flip-flop composed of two latches, and the output is opposite to the input. Opaque, the input must be reflected to the output only on the rising/falling edge of the clock, so the input glitch signal can be eliminated.

Comparison of flip-flops and latches:

1. Latch is triggered by level and controlled asynchronously. Latch is equivalent to the channel when the enable signal is valid, and the latch keeps the output state when the enable signal is invalid. DFF is triggered by a clock edge and controlled synchronously.

2. Latch is sensitive to the input level and is greatly affected by the wiring delay. It is difficult to ensure that the output is free of glitches; DFF is not easy to produce glitches.

3. If the gate circuit is used to build latch and DFF, the gate resource consumed by latch is less than that of DFF, which is the advantage of latch over DFF. Therefore, the integration level of using latch in ASIC is higher than that of DFF, but it is the opposite in FPGA, because there is no standard latch unit in FPGA, but there are DFF units, and a LATCH needs multiple LEs to realize. Latch is a level trigger, which is equivalent to an enable terminal, and after activation (when the level is enabled), it is equivalent to a wire and changes with the output. In the non-enabled state, the original signal is maintained. This can be seen from the difference with flip-flop. In fact, latch cannot replace ff in many cases.

4. Latch makes static timing analysis extremely complicated.

5. At present, latches are only used in very high-end power circuits, such as Intel’s P4 and other CPUs. There is a latch unit in FPGA, and the register unit can be configured as a latch unit. In the xilinx v2p manual, the unit becomes a register/latch unit. The attachment is the structure diagram of a half slice of xilinx.

The general design rule is: Avoid latches in most designs. It will make the timing of your design to an end, and its concealment is very strong, non-veterans can not find out. The biggest harm of latches is that they cannot filter burrs. This is extremely dangerous for the next-level circuit. Therefore, as long as the D flip-flop can be used, there is no need to latch.

In some places, there is no clock, so you can only use latch. For example, now use a clk to connect to the enable terminal of the latch (assuming it is high-level enable), so the required setup time is the time required for the data before the falling edge of the clock, but if it is a DFF, then the setup time is The time required on the rising edge of the clock. This means that if the data is later than the control signal, only the latch can be used. In this case, the latch timing borrow mentioned earlier. It is basically equivalent to borrowing a high level time. In other words, the time that the latch can borrow is also limited.

It is also possible to perform STA analysis on latches, but you need to be fairly familiar with the tools. But it is easy to make mistakes. Currently PrimeTime supports latch analysis. Now some integrated tools built-in STA analysis functions are also supported, such as RTL compiler, Design Compiler. In addition to saving resources in ASIC. The appearance of latch in the synchronization design is still quite small, and most of it is placed in ff in the process of processing.

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