【Introduction】With the help of wide-bandgap semiconductors, totem-pole power factor correction technology is becoming more and more mature, and when used in conjunction with SiC FETs with very low losses, it has reached its full potential.
Totem poles found on the Pacific Northwest coast of the United States have a range of uses, including decoration and commemoration, some welcome. I don’t know what picture picture that engineer was thinking when he named a “totem pole” a stack of two transistors driven in a complementary manner within a TTL logic circuit.
However, the term is now undoubtedly popular in the power world, using it to form a “totem pole” power factor correction stage. The totem-pole power factor correction stage is weakly related to the great engraving of the totem-pole, but the resemblance to the TTL output stage is obvious, with two sets of stacked switches, driven alternately, with one leg running at the AC line frequency and the other running at the AC line frequency. run at high frequency.
[Figure 1. Totem pole PFC circuit]
The key to this circuit arrangement is that it can be found through analysis that it is equivalent to a full-bridge AC rectifier followed by a power factor correction boost circuit, especially since there are fewer components on the power flow path and lower losses. Only two line AC rectifier diodes are required in the totem pole circuit, and even these two diodes can be replaced by synchronous rectifier MOSFETs for lower losses. Proportionally, the bridge rectifier can account for nearly 2% of the energy efficiency loss in the low-voltage line of the AC/DC converter. If the target energy efficiency of the end-to-end power supply can reach 96% to meet the 80+ titanium standard, it should be Work towards eliminating the 2%.
In a circuit, for one pole of the AC line, one switch (like Q1) conducts electricity and the other (Q2) blocks the current. This way, power goes into that pole, into Q3 and Q4, which form a classic PFC boost converter, where Q3 acts as a switch and Q4 operates as a synchronous rectifier to generate about 400V DC from standard mains. At the other AC line pole, Q2 conducts, Q1 blocks, and the opposite half-sine pole is routed to the boost converter, but now Q4 is the switch and Q3 is configured as a synchronous rectifier to generate the same high voltage DC rail. Due to the synchronous switch as a diode, the conduction losses of this circuit are limited only by the semiconductor on-resistance, Inductor resistance and connection resistance. For example, due to advances in switching technology, the RDS(on) value of MOSFETs now seems to make them ideal for low power to relatively high power circuits. One problem though, with silicon MOSFETs, dynamic losses can be so high that the circuit doesn’t work. The main problem is the power loss due to MOSFET body diode recovery when operating as a synchronous boost rectifier. There is always “dead time” between the MOSFET channel being effectively driven off and on to avoid cross-conduction, during which the entire body diode conducts through “commutation” while storing unwanted charge. This effect only occurs in “continuous conduction” mode, where the inductor current never drops to zero at any point during each switching cycle, but this mode is the preferred mode at higher powers, Peak and rms currents in switches and inductors can be controlled within specific ranges for low conduction losses.
Wide Bandgap Switching Enables a Viable Solution
For the above reasons, the totem-pole PFC stage, as an annoying topology, was bleak from its inception until the development of semiconductor technology and the birth of wide-bandgap semiconductors. The body diode reverse recovery charge of silicon carbide MOSFETs is much lower than that of silicon MOSFETs, and gallium nitride HEMT cells do not have this charge, so the age of this topology has come. Now we can realistically talk about achieving over 99% efficiency in the AC/DC front end, but there are still some difficulties with actual implementation as both SiC MOSFETs and GaN require very specific gate drive conditions to achieve efficiency to the last decimal and maintain reliability.
The gate drive problem has been addressed by incorporating UnitedSiC-fabricated SiC FETs in the design, which are cascode structures of SiC JFETs and silicon MOSFETs. The gate can now be driven at “normal” MOSFET or IGBT levels with a large safety margin from the absolute maximum +/- value, and a stable threshold level when the driving device is fully turned on, which is largely depends on time and temperature. However, there are other cases where the on-resistance of SiC FETs is much lower than that of SiC MOSFETs and GaN transistors at the same voltage level and the same die area, so the number of die per wafer is increased, and vice versa , under the condition of the same on-resistance, the die area will be smaller, which makes the device capacitance lower, and thus the switching loss is lower. The end result is lower overall losses, simple gate drive, and confidence that reliability is not compromised due to the lack of high-energy avalanche ratings in GaN devices.
The word totem pole comes from the Argonquin word “odoodem,” meaning “group of kin,” and it’s a good name for the combination of clever topology and near-ideal SiC FET switches.